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M-TDAT162G52-3BAL2 Scheda tecnica (PDF) - Agere Systems

M-TDAT162G52-3BAL2 Datasheet PDF - Agere Systems
Il numero della parte M-TDAT162G52-3BAL2
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Grandezza file   10822.88 Kbytes
Page   810 Pages
Produttore elettronici  AGERE [Agere Systems]
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Logo AGERE - Agere Systems
Spiegazioni elettronici MARS짰2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface

M-TDAT162G52-3BAL2 Datasheet (PDF)

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M-TDAT162G52-3BAL2 Datasheet PDF - Agere Systems

Il numero della parte M-TDAT162G52-3BAL2
Scarica  M-TDAT162G52-3BAL2 Click to download

Grandezza file   10822.88 Kbytes
Page   810 Pages
Produttore elettronici  AGERE [Agere Systems]
Homepage  
Logo AGERE - Agere Systems
Spiegazioni elettronici MARS짰2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface

M-TDAT162G52-3BAL2 Scheda tecnica (HTML) - Agere Systems

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M-TDAT162G52-3BAL2 Dettagli del prodotto

Description
The MARS2G5 P-Pro SONET/SDH interface device provides a versatile solution for quad OC-3, quad OC-12, and for single OC-48 linear datacom/telecom applications. Constructed using COM2 CMOS modular process, this device incorporates integrated SONET/SDH framing, section/line/path termination, pointer processing, and data engine blocks.

Features
■ One of the next-generation, system-on-a-chip devices of Agere Systems’ multiservice access & rate solutions MARSTM family of framers.
■ Transmission convergence and SONET/SDH terminal functionality for linear networks.
■ Versatile IC supports 155/622/2488 Mbits/s SONET/SDH interface solutions for packet over SONET (POS), packet over fiber (POF), or asynchronous transfer mode (ATM) applications.
■ Low-power 1.6 V/3.3 V operation.

SONET/SDH Interface
■ Termination of quad STS-3/STM-1, quad STS-12/STM-4, or single STS-48/STM-16.
■ Supports overhead processing for transport and path overhead bytes.
■ Optional insertion and extraction of overhead bytes via serial overhead interface.
■ STS pointer processing to align the receive frame to the system frame.
■ Support for 1 + 1 and 1:1 linear networks.
■ Full path termination and SPE extraction/insertion.
■ SONET/SDH compliant condition and alarm reporting.
■ Handles all concatenation levels of STS-3c to STS-48c (in multiples of 3: e.g., 3c, 6c, 9c, etc.).
■ Built-in diagnostic loopback modes.
■ Compliant with the following Telcordia Technologies®, ANSI®, and ITU standards:
    — GR-253 CORE: SONET Transport Systems: Common Generic Criteria.
    — ITU-T G.707: Network Node Interface for the Synchronous Digital Hierarchy.
    — ITU-T G.803: Architecture of Transport Networks Based on the Synchronous Digital Hierarchy.
    — T1.105: SONET-Basic Description including Multiplex Structure, Rates, and Formats.
    — T1.105.02 SONET-Payload Mappings.
    — T1.105.03 SONET-Jitter at Network Interfaces.
    — T1.105.06 SONET Physical Layer Specifications.
    — T1.105.07 SONET-Sub-STS-1 Interface Rates and Formats Specification.
    — ITU-T I.432: B-ISDN User-Network InterfacePhysical Layer Specification.
    — IETF RFC 2615: PPP over SONET/SDH.
    — IETF RFC 1661: The Point-to-Point Protocol (PPP).
    — IETF RFC 1662: PPP in HDLC-like Framing.

Data Processing
■ Provisionable data engine supports payload insertion/extraction for PPP, ATM, or HDLC streams.
■ Extraction and insertion of DS3 frames containing HDLC or ATM data streams for up to 16 channels.
■ Integrated UTOPIA Level 2 and Level 3 compatible physical layer interface for packets or ATM cells.
■ Provides/supports internal E3 mapping.
■ Supports DS3/PLCP and clear channel DS3 mapping.
■ Insertion and extraction of up to 16 separate data channels.
■ Direct cell/packet over fiber interface device.
■ Compliant with ATM forum, ITU standards, and IETF standards.
■ Supports generic framing procedure (GFP) protocol.

Interfaces
■ Enhanced UTOPIA interface for cell and packet transfer.
■ IEEE® 1149.1 port with BIST, scan, and boundry scan.

Microprocessor Interface
■ Up to 66 MHz synchronous.
■ 16-bit address and 16-bit data interface.
■ Synchronous or asynchronous modes available.
■ Configurable to operate with most commercial microprocessors.



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A proposito di Agere Systems


Agere Systems was a semiconductor company that specialized in providing integrated circuits (ICs) for telecommunications and storage applications. The company was founded in 2000 as a spin-off from Lucent Technologies, and was headquartered in Allentown, Pennsylvania, USA.

Agere Systems' product portfolio included ICs for wireless communication, networking, and storage applications. These products were used in a wide range of devices, including mobile phones, routers, switches, and data storage devices.

Agere Systems was known for its innovation and expertise in advanced semiconductor technologies, such as copper-based interconnects and silicon germanium (SiGe) technology. The company also had a strong focus on research and development, and held numerous patents in semiconductor design and manufacturing.

In 2005, Agere Systems was acquired by LSI Corporation, which later became part of Avago Technologies. Today, the technology and products developed by Agere Systems continue to be used in a variety of telecommunications and storage applications.

*Queste informazioni sono solo a scopo informativo generale, non saremo responsabili per eventuali perdite o danni causati dalle informazioni di cui sopra.




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