Overview The 3X38FTR 208-Pin SQFP is an eight-channel, single-chip complete transceiver designed specifically for dual-speed 10Base-T, 100Base-TX, and 100Base-FX switches and repeaters. It supports simultaneous operation in three separate IEEE * standard modes: 10Base-T, 100Base-TX, and 100Base-FX. The 3X38 uses 0.25 µm low-power CMOS to achieve extremely low power dissipation and operates from a single 3.3 V power supply. Features 10 Mbits/s Transceiver ■ Compatible with IEEE 802.3 10Base-T standard for category 3 unshielded twisted-pair (UTP) cable. ■ Compatible with the reduced MII (RMII) specification of the RMII consortium version 1.2. ■ Selectable 7-pin RMII or 2-pin serial MII (SMII). ■ Autopolarity detection and correction. ■ Adjustable squelch level for extended line length capability (two levels). ■ On-chip filtering eliminates the need for external filters. ■ Half- and full-duplex operations. 100 Mbits/s TX Transceiver ■ Compatible with IEEE 802.3u PCS (clause 23), PMA (clause 24), autonegotiation (clause 28), and PMD (clause 25) specifications. ■ Compatible with the reduced MII (RMII) specification of the RMII consortium version 1.2. ■ Selectable 7-pin RMII, 2-pin SMII (serial MII). ■ Scrambler/descrambler bypass. ■ Selectable carrier sense signal generation (CRS) asserted during either transmission or reception in half duplex (CRS asserted during reception only in full duplex). ■ Full- or half-duplex operations. ■ On-chip filtering and adaptive equalization that eliminates the need for external filters. 100 Mbits/s FX Transceiver ■ Pseudo-ECL compatible input/output for 100Base-FX support (with fiber-optic signal detect). ■ Compatible with IEEE 802.3u 100Base-FX standard. ■ Reuses existing twisted-pair I/O pins for compatible fiber-optic transceiver pseudo-ECL (PECL) data: — No additional data pins required. — Reuses existing 3X38 pins for fiber-optic signal detect (FOSD) inputs. ■ Fiber mode automatically configures port: — Disables autonegotiation. — Disables 10Base-T. — Enables 100Base-FX far-end fault signaling. — Disables MLT-3 encoder/decoder. — Disables scrambler/descrambler. ■ FX mode enable is pin- or register-selectable on an individual per-port basis. General ■ Low power dissipation (<0.4 W per port). ■ Autonegotiation (IEEE 802.3u, clause 28): — Fast link pulse (FLP) burst generator. — Arbitration function. ■ Supports the station management protocol and frame format (clause 22): — Basic and extended registers. — Supports next page mode. — Accepts preamble suppression. — Maskable status interrupts. — 12.5 MHz MDC clock rate. ■ Supports the following management functions via pins if MII station management is unavailable: — Speed select. — Scrambler/descrambler bypass. — Full duplex. — No link pulse mode. — Carrier sense select. — Autonegotiation. — FX mode select. ■ Single 50 MHz/125 MHz clock input in RMII and SMII modes, respectively. ■ Supports half- and full-duplex operations. ■ Provides four LED status signals: — Activity (transmit or receive). Optional LED blink mode (500 ms on, 500 ms off or 2.5 s on, 2.5 s off) or pulse stretch mode (40 ms—80 ms). — Full duplex or collision, automatically configured. — Link integrity. — Speed indication. ■ Internally generated power-on-reset configures 3X38 automatically on powerup. ■ Serial LED output stream for additional status monitoring. ■ Bicolor LED mode. ■ LED drivers on-chip (8 mA—10 mA). Drivers can be turned off when LED is not used (power saving). ■ Per-channel powerdown mode for 10 Mbits/s and 100 Mbits/s operation. ■ Loopback for 10 Mbits/s and 100 Mbits/s operation. ■ Internal pull-up or pull-down resistors to set default configuration during powerup. ■ 0.25 µm low-power CMOS technology. ■ 208-pin SQFP package. ■ JTAG boundary scan. ■ Single 3.3 V power supply
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