Description
The 8Gb (TwinDie) DDR3L SDRAM (1.35V) uses two Micron 4Gb DDR3L SDRAM x8 die for a 2 byte x16 de- vice in one package. Refer to Micron’s 4Gb DDR3L SDRAM data sheet (x8 option) for specifications not included in this document, specifications for base part number MT41K512M8 correlate to TwinDie manufac- turing base part number MT41K512M16.

Features
* Uses two x8, 4Gb Micron die to make one x16 pack-age
-”Single rank TwinDie
- One external ZQ ball and one internal ZQ connected to Vssq through an embedded serial resis-tor
Vpp =Vppg = 1.35V (1.283-1.45V)
Backward compatible to Vpp =Vppq = 1.5V £0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable posted CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
Tcof-40°C to +105°C
- 64ms, 8192-cycle refresh at-40°C to +85°C
- 32ms at +85°C to +105°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multipurpose register
Output driver calibration
AEC-Q100
PPAP submission
8D response time