L9680 datasheet(251/277 Pages) STMICROELECTRONICS

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L9680

Electrical characteristics

276

CSSxy

SSxy Capacitance

Maximum capacitance to GND

connected directly to SSxy pin

Design Information

RSFLx

Load Impedance

Design Info

6.5

Wire Length

Squib Loops containing a clock

spring shall be limited to a

maximum length of 3m

RWirex

Wire Resistance

Design Info

16.8

63.4

mΩ/

LWirex

Wire Inductance

Design Info

0.6

1.8

μH/

RCSx

Clock Spring Resistance

Maximum number of clock

springs is 3 for any IC

Design Info

0.7

LCSx

Clock Spring Inductance

Design Info

42.9

μH

kL_CS1 –

L_CS2

Clock Spring Coupling

Design Info

0.739

0.903

LEMI

Squib EMI protection

Design Info

7.7

μH

In case of an unsupplied device and shorted deployment pins (e.g. to battery voltage), the dynamic reverse current through

the high side power stage depends on CSSxy.

2. LDEPL could be calculated in the following way:

Non-Clock Spring Loops: LDEPL(max) = LWire(10m*2) + LEMI = (3.6uH/m * 10m) + 7.7uH =43.7uH

Clock Spring Loops: LWire(3m*2) + 2*LCSx + LEMI - (2*kL_CX*SQRT(L_CS1*L_CS2)) = = (3.6uH/m * 3m) + 2 * 42.9uH + 7.7uH -

(2 * 0.739 * 42.9uH) = 40.9uHClock Spring Loops with short to ground

LDEPL(max) = LWire(3m) + LCSx + LEMI = (1.8uH/m * 3m) + 42.9uH + 7.7uH = 56uH.

Table 55. Deployment drivers – DC specifications (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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