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AM652X Scheda tecnica(PDF) 157 Page - Texas Instruments |
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AM652X Scheda tecnica(HTML) 157 Page - Texas Instruments |
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157 / 299 page  RGMII[x] RXD _ [3:0] (B) RGMII[x] RCTL _ (B) RGMII[x] RXC _ (A) RGMII5 RXERR RXDV 1st Half-byte 2nd Half-byte RGRXD[7:4] RGRXD[3:0] RGMII2 RGMII3 RGMII1 RGMII4 RGMII4 RGMII6 SPRSP08_CPSW2G_RGMIIRX 157 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Table 5-34. Timing Requirements for RGMII[x]_RCLK - RGMII Mode (continued) NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII2 tw(RXCH) Pulse duration, RXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(RXCL) Pulse duration, RXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII4 tt(RXC) Transition time, RXC 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns Table 5-35. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode NO. PARAMETER DESCRIPTION MODE MIN TYP MAX UNIT RGMII5 tsu(RD-RXC) Setup time, RD[3:0] valid before RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns tsu(RX_CTL-RXC) Setup time, RX_CTL valid before RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII6 th(RXC-RD) Hold time, RD[3:0] valid after RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns th(RXC-RX_CTL) Hold time, RX_CTL valid after RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII7 tt(RD) Transition time, RD 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns tt(RX_CTL) Transition time, RX_CTL 10Mbps 0.75 ns 100Mbps 0.75 ns 1000Mbps 0.75 ns A. RGMII_RXC must be externally delayed relative to the data and control pins. B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC and RXERR on falling edge of RGMII_RXC. Figure 5-32. CPSW2G Receive Interface Timing, RGMII operation |
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