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DSP56857 Scheda tecnica(PDF) 203 Page - Freescale Semiconductor, Inc |
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DSP56857 Scheda tecnica(HTML) 203 Page - Freescale Semiconductor, Inc |
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203 / 662 page ![]() Register Descriptions (ITCN_BASE = $1FFF20) Overview, Rev. 4 Freescale Semiconductor 8-25 8.7.9.4 Receiver Idle Interrupt Priority Level (SCI1_RIDL IPL)—Bits 5–4 These fields are used to set the interrupt priority levels for certain peripheral IRQs. These IRQs are limited to priorities zero through two and are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 8.7.9.5 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—Bits 3–2 These fields are used to set the interrupt priority levels for certain peripheral IRQs. These IRQs are limited to priorities zero through two and are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 8.7.9.6 Transmitter Empty Interrupt Priority Level (SCI1_XMIT IPL) —Bits 1–0 These fields are used to set the interrupt priority levels for certain peripheral IRQs. These IRQs are limited to priorities zero through two and are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 8.7.10 Vector Base Address Register (VBA) Figure 8-12. Vector Base Address Register (VBA) See Programmer’s Sheet on Appendix page B - 37 Base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 VECTOR_BASE_ADDRESS Write Reset 0 0 00000 00 0 000 000 |
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