DSP56857 datasheet(249/662 Pages) FREESCALE

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Functional Description

Serial Communications Interface (SCI), Rev. 4

Freescale Semiconductor

10-13

If Start bit verification is not successful, the RT clock is reset and a new search for a Start bit

begins.

To determine the value of a Data bit and to detect noise, recovery logic takes samples at RT8,

RT9, and RT10. Table 10-8 summarizes the results of the Data bit samples.

Note:

The RT8, RT9, and RT10 samples do not affect Start bit verification. If any or all of

the RT8, RT9, and RT10 Start bit samples are logic 1s following a successful Start bit

verification, the Noise Flag (NF) is set and the receiver assumes that the bit is a Start

bit (Logic 0).

To verify a Stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10.

Table 10-9 summarizes the results of the Stop bit samples.

Figure 10-7 illustrates the verification samples RT3 and RT5 determine the first low detected

was noise and not the beginning of a Start bit. The RT clock is reset and the Start bit search

begins again. The Noise Flag is not set because the noise occurred before the Start bit was found.

Table 10-8. Data Bit Recovery

RT8, RT9, and RT10

Samples

Data Bit

Determination

Noise

Flag

000

001

010

011

100

101

110

111

Table 10-9. Stop Bit Recovery

RT8, RT9, and RT10

Samples

Framing Error

Flag

Noise

Flag

000

001

010

011

100

101

110

111

DSP56857 Scheda tecnica(PDF) 249 Page - Freescale Semiconductor, Inc

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