DSP56857 datasheet(298/662 Pages) FREESCALE

298 / 662 page

Resets

5685X Digital Signal Controller User Manual, Rev. 4

11-28

Freescale Semiconductor

11.11.3 SPI Data Receive Register (SPDRR)

This read-only register will show the last full data received after a complete transmission while

the SPRF bit will set when new data has been transferred to this register.

Figure 11-16. SPI Data Receive Register (SPDRR)

See Programmer’s Sheets on Appendix page B-66

11.11.3.1 Data Receive—Bits 15–0

11.11.4 SPI Data Transmit Register (SPDTR)

This write-only register modifies the data to the transmit data buffer. When the SPTE bit is set,

new data should be written to this register. If new data is not written while in the Master mode, a

new transaction will not be initiated until this register is written. When in Slave mode, the old

data will be re-transmitted. All data should be written with the LSB at bit zero.

Figure 11-17. SPI Data Transmit Register (SPDTR)

See Programmer’s Sheets on Appendix page B-67

11.11.4.1 Data Transmit—Bits 15–0

11.12 Resets

Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit

(SPE) is low. Whenever SPE is low, the following will occur:

•

The SPTE flag is set.

•

Any slave mode transmission currently in progress is aborted.

•

Any master mode transmission currently in progress is continued to completion.

•

The SPI state counter is cleared, making it ready for a new complete transmission.

•

All the SPI port logic is disabled.

Base + $2

Read

R15

R14

R13

R12

R11

R10

Write

Reset

000

Base + $3

Read

Write

T15

T14

T13

T12

T11

T10

Reset

0000

00000

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