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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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DSP56857 Scheda tecnica(PDF) 482 Page - Freescale Semiconductor, Inc |
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DSP56857 Scheda tecnica(HTML) 482 Page - Freescale Semiconductor, Inc |
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482 / 662 page  TAP Controller 5685X Digital Signal Controller User Manual, Rev. 4 17-20 Freescale Semiconductor Figure 17-7. TAP Controller State Diagram The TAP Controller will execute the last instruction decoded until a new instruction is entered at the Update-IR state, or Test-Logic-Reset is entered. There are two paths through the 16-state machine. The shift-IR-scan path captures and loads JTAG instructions into the JTAGIR. The shift-DR-scan path captures and loads data into the other JTAG registers. The TAP Controller executes the last instruction decoded until a new instruction is entered at the update-IR state, or until the test-logic-reset state is entered. When using the JTAG port to access EOnCE module registers, follow these four steps: 1. Enable the TLM by shifting the TLM_SEL instruction into the JTAGIR. 2. When selected, the TLM must enable the 56800E TAP by shifting in the appropriate value into the TLM register. 3. When the 56800E TAP is selected, the EOnCE module is selected by shifting the ENABLE_EOnCE instruction. 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 0 0 00 0 0 0 0 0 0 0 0 0 Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR Select-IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR Select-DR-Scan 7 6 2 1 3 0 5 D 8 B 9 A E 4 Test-Logic-Reset F Run-Test/Idle C |
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