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DSP56857 Scheda tecnica(PDF) 646 Page - Freescale Semiconductor, Inc |
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DSP56857 Scheda tecnica(HTML) 646 Page - Freescale Semiconductor, Inc |
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646 / 662 page  Application: Date: Programmer: Sheet Appendix B - Programmer’s Sheets, Rev. 4 Freescale Semiconductor B-144 Preliminary HI8 8 of 10 Bits Name Description 7 - 0 IV7 - IV0 Interrupt Vector This read/write register typically containing the interrupt vector number used with MC68000 family processor vectored interrupts. Only the host processor can read and write this register. The contents of IVR are placed on the Host data bus (H0–H7) when both HREQ and HACK pins are asserted and Host DMA is not enabled. The contents of this register are initialized to a pre-defined value by a hardware or software reset, corresponding to the uninitialized interrupt vector in the MC68000 family. HI8 Interrupt Vector Register (IVR) HI8 Interrupt Vector Register (IVR) $1FFFD8 + $3 Bits 7 6 5 4 3 2 1 0 Read IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0 Write Reset 0 000 11 11 |
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