XRT7250 datasheet(310/463 Pages) EXAR

310 / 463 page

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XRT7250

DS3/E3 FRAMER IC

REV. 1.1.1

291

When the Receive E3 Framer block detects the FAS

pattern, it will then transition over to the FAS Pattern

Verification state, per Figure 137.

The FAS Pattern Verification State

Once the Receive E3 Framer block has detected an

“1111010000” pattern, it must verify that this pattern

is indeed the FAS pattern and not some other set of

bits, within the E3 frame, mimicking the FAS Pattern.

FIGURE 136. THE STATE MACHINE DIAGRAM FOR THE RECEIVE E3 FRAMER E3 FRAME ACQUISITION/MAINTENANCE

ALGORITHM

FAS

Pattern

FAS

Pattern

Verification

In Frame

OOF

Condition

LOF

Condition

FAS pattern is

detected once

FAS Pattern is

verified once

FAS Pattern is

not detected

4 consecutive

In-valid Frames

3 consecutive

Valid Frames

8 or 24 framing periods

of operating in the

OOF condition

(user-selectable)

Frame Maintenance

Mode

FIGURE 137. ILLUSTRATION OF THE E3, ITU-T G.751 FRAMING FORMAT

Frame

Alignment

Signal

Data

BIP-4

if Selected

384 385

768

769

1152 1153

1532

1536

Framing Alignment Signal Pattern = 1111010000

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