VSC7440 datasheet(425/444 Pages) MICROSEMI

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Pin Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

408

7.2.11

Serial CPU Interface

The serial CPU interface (SI) can be used as a serial slave, master, or boot interface.

As a slave interface, it allows external CPUs to access internal registers. As a master interface, it allows

the device to access external devices using a programmable protocol. The serial CPU interface also

allows the internal VCore-III CPU system to boot from an attached serial memory device when the

VCore_CFG signals are set appropriately.

The following table lists the pins associated with the serial CPU interface (SI).

7.2.12

System Clock Interface

The following table lists the pins associated with the system clock interface.

S[10:9]_TXN

S[10:9]_TXP

CML

Differential data outputs.

10G/2.5G/1G.

S[8:7]_RXN

S[8:7]_RXP

CML

Differential data inputs.

10G/2.5G/1G.

S[8:7]_TXN

S[8:7]_TXP

CML

Differential data outputs.

10G/2.5G/1G.

Table 335 •

Serial CPU Interface Pins

Name

I/O

Type

Level

Description

SI_CLK

I/O

ST, 3V

LVCMOS Slave mode: Input receiving serial interface clock from external master.

Master mode: Output driven with clock to external device.

Boot mode: Output driven with clock to external serial memory device.

SI_DI

ST, 3V

LVCMOS Slave mode: Input receiving serial interface data from external master.

Master mode: Input data from external device.

Boot mode: Input boot data from external serial memory device.

SI_DO

OZ, 3V

LVCMOS Slave mode: Output transmitting serial interface data to external

master.

Master mode: Output data to external device.

Boot mode: Output boot control data to external serial memory device.

SI_nCS0

I/O

ST, 3V

LVCMOS Slave mode: Input used to enable SI slave interface.

0 = Enabled

1 = Disabled

Master mode: Output driven low while accessing external device.

Boot mode: Output driven low while booting from EEPROM or serial

flash to internal VCore-III CPU system. Released when booting is

completed.

Table 336 •

System Clock Interface Pins

Name

I/O

Type

Level

Description

CLKOUTPLL_N

CLKOUTPLL_P

LVDS

PLL clock output. Leave floating if not used.

Table 334 •

SERDES10G Pins (continued)

Name

I/O

Type

Level

Description

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