KSZ8563R datasheet(134/221 Pages) MICROCHIP

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KSZ8563R

DS00002418D-page 134

 2017-2018 Microchip Technology Inc.

5.2.2

PORT N: PORT ETHERNET PHY REGISTERS (0xN100 - 0xN1FF)

The registers in this section are for PHY ports only. Refer to the IEEE802.3 clause 22.3.4 for additional details.

5.2.2.1

PHY Basic Control Register

PHY register 0x00.

Receive Flow Control Enabled Status

For non-PHY ports, this bit duplicates the Rx FC enable bit 3 in the XMII Port

Control 0 Register.

For PHY ports, this bit is set only when FC is enabled (PHY Auto-Negotiation

Advertisement Register, bits 11:10), link is up and FC is established via auto-

negotiation.

1 = RX flow control is enabled

0 = Disabled

Address:

0xN100 - 0xN101

Port N: 1-2

Size:

16 bits

Bits

Description

Type

Default

PHY Software Reset

Set this bit to reset this PHY. Registers are not reset. This bit is self-clearing.

R/W

Local Loopback Mode

Data going from the internal switch fabric to an egress port is looped back at

that egress port and returned to the internal switch fabric.

1 = Local Loopback mode

0 = Normal operation

R/W

Speed Select (LSB)

This bit is ignored if auto-negotiation is enabled (bit 12 in this register).

1 = 100 Mb/s

0 = 10 Mb/s

R/W

Note 5-4

Auto-Negotiation Enable

1 = Auto-negotiation is enabled

0 = Auto-negotiation is disabled

The initial value of this bit is determined by a strapping option, but it may be

overwritten.

R/W

Note 5-4

Power Down

1 = Power-down mode

0 = Normal operation

When this bit is set to ‘1’, the link-down status might not get updated in the

PHY status register. Software should note link is down and should not rely on

the PHY status register link status.

After this bit is changed from ‘1’ to ‘0’, an internal reset is performed. Wait a

minimum of 1ms before read/write access to this PHY’s registers.

R/W

Bits

Description

Type

Default

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