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KSZ8563R Scheda tecnica(PDF) 173 Page - Microchip Technology

Il numero della parte KSZ8563R
Spiegazioni elettronici  3-Port 10/100 Ethernet Switch with RGMII/MII/RMII Interface and IEEE 1588v2
PDF  221 Pages
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Produttore elettronici  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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KSZ8563R Scheda tecnica(HTML) 173 Page - Microchip Technology

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DS00002418D-page 173
KSZ8563R
5.2.10.2
Port MSTP Pointer Register
5.2.10.3
Port MSTP State Register
There are eight MSTPs, and the MSTP Pointer in the Port MSTP Pointer Register is used as an index to select a par-
ticular MSTP when reading or writing this register.
5.2.11
PORT N: PORT SWITCH PTP CONTROL REGISTERS (0xNC00 - 0xNCFF)
5.2.11.1
Port PTP Receive Latency Register
Address:
0xNB01
Port N: 1-3
Size:
8 bits
Bits
Description
Type
Default
7:3
RESERVED
R/W
0000_0b
2:0
MSTP Pointer
Points to one of the 8 MSTPs. It is used as an index when reading or writing
the Port MSTP State Register.
R/W
000b
Address:
0xNB04
Port N: 1-3
Size:
8 bits
Bits
Description
Type
Default
7:3
RESERVED
RO
0000_0b
2
Port Transmit Enable
1 = Enable packet transmission on the port
0 = Disable packet transmission on the port
R/W
1b
1
Port Receive Enable
1 = Enable packet reception on the port
0 = Disable packet reception on the port
R/W
1b
0
Port Learning Disable
1 = Disable switch address learning on the port
0 = Enable switch address learning on the port
R/W
0b
Address:
0xNC00 - 0xNC01
Port N: 1-3
Size:
16 bits
Bits
Description
Type
Default
15:0
PTP Port N RX Latency in Nanoseconds (PTP_RX_LATENCY[15:0])
This field is used to set the fixed receive delay value from the port N wire to
the RX timestamp reference point. The default value is 415ns.
R/W
0x019F



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