HCS08 datasheet(174/374 Pages) NXP

174 / 374 page

MC9S08JM60 Series Data Sheet, Rev. 5

174

Freescale Semiconductor

11.6.2

Address Detect Interrupt

When the calling address matches the programmed slave address (IIC address register) or when the

GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is

interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly.

11.6.3

Arbitration Lost Interrupt

The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more

masters try to control the bus at the same time, the relative priority of the contending masters is determined

by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration

process and the ARBL bit in the status register is set.

Arbitration is lost in the following circumstances:

•

SDA sampled as a low when the master drives a high during an address or data transmit cycle.

•

SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive

cycle.

•

A start cycle is attempted when the bus is busy.

•

A repeated start cycle is requested in slave mode.

•

A stop condition is detected when the master did not request it.

This bit must be cleared by software writing a 1 to it.

HCS08 Scheda tecnica(PDF) 174 Page - NXP Semiconductors