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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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SC3200 Scheda tecnica(PDF) 104 Page - Advanced Micro Devices |
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SC3200 Scheda tecnica(HTML) 104 Page - Advanced Micro Devices |
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104 / 447 page  104 AMD Geode™ SC3200 Processor Data Book General Configuration Block Revision 5.1 Offset 1Eh-1Fh Core Clock Frequency Control Register - CCFC (R/W) Reset Value: Strapped Value This register controls the configuration of the core clock multiplier and the reference clocks. 15:14 Reserved. 13 Reserved. Must be set to 0. 12 Reserved. Must be set to 0. 11:10 Reserved. 9:8 FPCICK (Internal Fast-PCI Clock). (Read Only) Reflects the internal Fast-PCI clock and is the input to the GX1 module that is used to generate the core clock. These bits reflect the value of strap pins CLKSEL[1:0]. 00: 33.3 MHz 01: 48 MHz 10: 66.7 MHz 11: 33.3 MHz 7:4 Reserved. 3:0 MVAL (Multiplier Value). This 4-bit value controls the multiplier in ADL. The value is set according to the Maximum Clock Multiplier bits of the MCCM register (Offset 10h). The multiplier value should never be written with a multiplier which is differ- ent from the multiplier indicated in the MCCM register. 0100: Multiply by 4 0101: Multiply by 5 0110: Multiply by 6 0111: Multiply by 7 1000: Multiply by 8 1001: Multiply by 9 1010: Multiply by 10 Other: Reserved Table 4-8. Clock Generator Configuration (Continued) Bit Description |
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