STM32L072CB datasheet(158/160 Pages) STMICROELECTRONICS

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Revision history

STM32L072xx

158/160

DS10689 Rev 5

13-Sep-2017

Memories and I/Os moved after Core in Features.

Table 2: Ultra-low-power STM32L072xx device features and

peripheral counts: changed number of USART for

LQFP32/UFQFPN32 and added note 3.

Removed column "I/O operation" from Table 3: Functionalities

depending on the operating power supply range and added note

related to GPIO speed.

Updated VDD_USB in Section 3.4.1: Power supply schemes.

In Section 4: Pin descriptions, renamed USB_OE into USB_NOE.

In Section 5: Memory mapping, replaced memory mapping

schematic by reference to the reference manual.

Updated Figure 7: STM32L072xx WLCSP49 ballout.

Added mission profile compliance with JEDEC JESD47 in

Section 6.2: Absolute maximum ratings.

Updated minimum and maximum values of I/O weak pull-up

equivalent resistor (RPU) and weak pull-down equivalent resistor

(RPD) in Table 60: I/O static characteristics.

Updated minimum and maximum values of NRST weak pull-up

equivalent resistor (RPU) in Table 63: NRST pin characteristics.

Added note 2. related to the position of the external capacitor below

Figure 29: Recommended NRST pin protection.

Updated RAIN in Table 64: ADC characteristics.

Updated Figure 34: 12-bit buffered/non-buffered DAC and added

note below figure.

Updated tAF maximum value for range 1 in Table 73: I2C analog filter

characteristics.

Removed Table 90: USART/LPUART characteristics.

NSS timing waveforms updated in Figure 35: SPI timing diagram -

slave mode and CPHA = 0 and Figure 36: SPI timing diagram - slave

mode and CPHA = 1(1).

Updated Figure 53: TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin

profile fine pitch ball grid array package outline.

Added reference to optional marking or inset/upset marks in all

package device marking sections.

Updated note below marking schematics.

Table 96. Document revision history (continued)

Date

Revision

Changes

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