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STM32WB10CC Scheda tecnica(PDF) 102 Page - STMicroelectronics |
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STM32WB10CC Scheda tecnica(HTML) 102 Page - STMicroelectronics |
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102 / 110 page  Electrical characteristics STM32WB10CC 102/110 DS13259 Rev 2 JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 77 and Table 78 are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions summarized in Table 20: General operating conditions. with the following configuration: Capacitive load C = 30 pF Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.16 for more details on the input/output alternate function characteristics (CK, SD, WS). Table 77. JTAG characteristics Symbol Parameter Conditions Min Typ Max Unit 1/tc(TCK) TCK clock frequency 2.7 < VDD < 3.6 V - - 29 MHz 2.0 < VDD < 3.6 V - - 21 tisu(TMS) TMS input setup time - 2.5 - - ns tih(TMS) TMS input hold time - 2.0 - - tisu(TDI) TDI input setup time - 2.0 - - tih(TDI) TDI input hold time - 2.0 - - tov(TDO) TDO output valid time 2.7 < VDD < 3.6 V - 13.5 16.5 2.0 < VDD < 3.6 V - 13.5 23.0 toh(TDO) TDO output hold time - 11.0 - - Table 78. SWD characteristics Symbol Parameter Conditions Min Typ Max Unit 1 / tc(SWCLK) SWCLK clock frequency 2.7 < VDD < 3.6 V - - 55 MHz 2.0 < VDD < 3.6 V - - 35 tisu(TMS) SWDIO input setup time - 2.5 - - ns tih(TMS) SWDIO input hold time - 2.0 - - tov(TDO) SWDIO output valid time 2.7 < VDD < 3.6 V - 16 18 2.0 < VDD < 3.6 V - 16 28 toh(TDO) SWDIO output hold time - 13 - - |
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