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acquisition frequency. The designer must understand the time required for the source impedance of each ADC0_AIN pin to charge the

internal sampling capacitor. The acquisition time must be set long enough for the internal sampling capacitor to settle to greater than

14 bits of accuracy.

(3)

ADC0 can be configured to operate in General Purpose Input mode, where all ADC0_AIN[7:0] inputs are globally enabled to operate

as digital inputs via the ADC0_CTRL register (gpi_mode_en = 1).

7.7.8 USB2PHY Electrical Characteristics

Note

USB0 interface is compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000

including ECNs and Errata as applicable.

7.7.9 SerDes PHY Electrical Characteristics

Note

The PCIe interface is compliant with the electrical parameters specified in PCI Express® Base

Specification Revision 4.0, February 19, 2014.

Note

USB0 instance is compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative

Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July

26, 2013.

7.7.10 DDR Electrical Characteristics

Note

The DDR interface is compatible with DDR4 and LPDDR4 devices

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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