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AM2434...ALV Scheda tecnica(PDF) 156 Page - Texas Instruments

Il numero della parte AM2434...ALV
Spiegazioni elettronici  AM243x Sitara™ Microcontrollers
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AM2434...ALV Scheda tecnica(HTML) 156 Page - Texas Instruments

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7.10.5.2 DDRSS
For more details about features and additional description information on the device (LP)DDR4 Memory
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 7-34 and Figure 7-28 present switching characteristics for DDRSS.
Table 7-34. DDRSS Switching Characteristics
see Figure 7-28
NO.
PARAMETER
DDR TYPE
MIN
MAX
UNIT
1
tc(DDR_CKP/
DDR_CKN)
Cycle time, DDR_CKP and DDR_CKN
LPDDR4
1.25(1)
20
ns
DDR4
1.25(1)
1.6
ns
(1)
Minimum DDR clock Cycle time will be limited based on the specific memory type (vendor) used in a system and by PCB
implementation. Refer to AM64x\AM243x DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve
maximum DDR frequency.
DDR0_CKP
1
DDR0_CKN
Figure 7-28. DDRSS Switching Characteristics
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.
AM2434, AM2432, AM2431
SPRSP65D – APRIL 2021 – REVISED AUGUST 2022
www.ti.com
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