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STM32F405 Scheda tecnica(PDF) 123 Page - STMicroelectronics |
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STM32F405 Scheda tecnica(HTML) 123 Page - STMicroelectronics |
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123 / 204 page ![]() DS8626 Rev 9 123/203 STM32F405xx, STM32F407xx Electrical characteristics tw(SCKH) SCK high and low time Master mode, SPI presc = 2, 2.7V < VDD < 3.6V TPCLK-0.5 TPCLK TPCLK+0.5 ns tw(SCKL) Master mode, SPI presc = 2, 1.7V < VDD < 3.6V TPCLK-2 TPCLK TPCLK+2 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4 x TPCLK -- th(NSS) NSS hold time Slave mode, SPI presc = 2 2 x TPCLK tsu(MI) Data input setup time Master mode 6.5 - - tsu(SI) Slave mode 2.5 - - th(MI) Data input hold time Master mode 2.5 - - th(SI) Slave mode 4 - - ta(SO)(2) Data output access time Slave mode, SPI presc = 2 0 - 4 x TPCLK tdis(SO)(3) Data output disable time Slave mode, SPI1, 2.7V < VDD < 3.6V 0- 7.5 Slave mode, SPI1/2/3 1.7V < VDD < 3.6V 0- 16.5 tv(SO) th(SO) Data output valid/hold time Slave mode (after enable edge), SPI1, 2.7V < VDD < 3.6V -11 13 Slave mode (after enable edge), SPI2/3, 2.7V < VDD < 3.6V -12 16.5 Slave mode (after enable edge), SPI1, 1.7V < VDD < 3.6V - 15.5 19 Slave mode (after enable edge), SPI2/3, 1.7V < VDD < 3.6V -18 20.5 tv(MO) Data output valid time Master mode (after enable edge), SPI1, 2.7V < VDD < 3.6V -- 2.5 Master mode (after enable edge), SPI1/2/3, 1.7V < VDD < 3.6V -- 4.5 th(MO) Data output hold time Master mode (after enable edge) 0 - - 1. Guaranteed by characterization. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Table 55. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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