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STM32F405RG Scheda tecnica(PDF) 146 Page - STMicroelectronics |
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STM32F405RG Scheda tecnica(HTML) 146 Page - STMicroelectronics |
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146 / 201 page  Electrical characteristics STM32F405xx, STM32F407xx 146/201 DocID022152 Rev 6 Synchronous waveforms and timings Figure 58 through Figure 61 represent synchronous waveforms and Table 80 through Table 82 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 60 MHz). tv(Data_NADV) FSMC_NADV high to Data valid - THCLK–0.5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK -ns 1. CL = 30 pF. 2. Guaranteed by characterization. Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) |
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