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STM32F103ZCT7XXX Scheda tecnica(PDF) 109 Page - STMicroelectronics |
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STM32F103ZCT7XXX Scheda tecnica(HTML) 109 Page - STMicroelectronics |
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109 / 143 page  DS5792 Rev 13 109/143 STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 135 Figure 58. Typical connection diagram using the ADC 1. Refer to Table 59 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 59 or Figure 60, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 59. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are available only on 100-pin packages. |
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