XIO2000 datasheet(123/150 Pages) TI

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Memory-Mapped TI Proprietary Register Space

111

November 2005

SCPS097B

6.4

Upstream Isochrony Control Register

The upstream isochrony control register allows software to control bridge isochronous behavior. See

Table 6−3 for a complete description of the register contents.

Device control memory window register offset:

04h

Read-only, Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 6−3. Upstream Isochrony Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:3

RSVD

Reserved. Returns 0 0000 0000 0000b when read.

PORTARB_LEVEL_2_EN

Port arbitration level 2 enable. This bit is only valid if PORTARB_LEVEL_1_EN is set to

1b, because this enhances the behavior enabled through the assertion of that bit. If

PORTARB_LEVEL_1_EN is clear, then this bit is read-only and returns 0b when read.

0 = Arbiter behavior follows PORTARB_LEVEL_1_EN rules (default)

1 = Aggressive mode. The arbiter deliberately stops secondary bus masters in the

middle of their transaction to assure that isochrony is preserved.

PORTARB_LEVEL_1_EN

Port arbitration level 1 enable.

0 = Arbiter behavior is controlled only by the arbiter control registers within the classic

PCI configuration space (default)

1 = Values programmed within the port arbitration table for extended VCs impact the

arbiter’s decision to assert GNT to any particular bus master. Programmed values

in the arbiter control registers within the classic PCI configuration space have no

effect when this bit is asserted.

ISOC_ENABLE

Isochronous enable. Global enable bit for the upstream isochronous capability of the

bridge.

0 = Mapping of upstream traffic to TCs other than TC0 prohibited (default)

1 = Mapping of upstream traffic to TCs other than TC0 permitted

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