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MPC8540 Scheda tecnica(PDF) 215 Page - Freescale Semiconductor, Inc

Il numero della parte MPC8540
Spiegazioni elettronici  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Produttore elettronici  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Scheda tecnica(HTML) 215 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
5-1
Chapter 5
Core Complex Overview
This chapter provides an overview of the PowerPC e500 microprocessor core as it is implemented
on the MPC8540.
This chapter includes the following:
•
An overview of the Book E version of the PowerPC architecture features as implemented
in this core and a summary of the core feature set
•
A summary of the instruction pipeline and flow
•
An overview of the programming model
•
An overview of interrupts and exception handling
•
A description of the memory management architecture
•
High-level details of the e500 core memory and coherency model
•
A brief description of the core complex bus (CCB)
•
A summary of the Book E architecture compatibility and migration from the original
version of the PowerPC architecture as it is defined by Apple, IBM, and Motorola (referred
to as the AIM version of the PowerPC architecture)
Specific details about the e500 are provided in the PowerPC e500 Core Complex Reference
Manual (Freescale Semiconductor Document ID No. E500CORERM). The e500 core provides
features that the integrated device may not implement or may implement in a more specific way.
These differences are summarized in Section 5.14, “PowerQUICC III Implementation Details.”
5.1
Overview
The e500 processor core is a low-power implementation of the family of reduced instruction set
computing (RISC) embedded processors that implement the Book E definition of the PowerPC
architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words
in the 64-bit general-purpose registers (GPRs).
Figure 5-1 is a block diagram of the processor core complex that shows how the functional units
operate independently and in parallel. Note that this conceptual diagram does not attempt to show
how these features are physically implemented.



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