TDA4VE...ALZQ1 datasheet(104/251 Pages) TI

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7.5 Operating Performance Points

This section describes the operating conditions of the device. This section also contains the description of each

Operating Performance Point (OPP) for processor clocks and device core clocks.

Table 7-1 describes the maximum supported frequency per speed grade for the device.

Table 7-1. Speed Grade Maximum Frequency

DEVICE

MAXIMUM FREQUENCY (MHz)

A72SS0

C71SS0/1

R5FSS0/1

MCU_

R5SS0

GPU

CBASS0

VPAC

DMPAC

VENCDEC

DMSC

LPDDR4

2000

1000

800

500

720(1)

520(1)

550

(480MP/s)

333

4266 MT/

s(2)

1600

750

1000

800

500

600 (1)

433 (1)

275

(240MP/s)

333

3733 MT/s

(2)

1200

500

1000

800

500

600 (1)

300 (1)

275 (240

MP/s)

333

3200 MT/s

(2)

(1)

Max VPAC and DMPAC speeds not available concurrently due to PLL sharing (max combinations are 720/480 and 650/520 for

VPAC/DMPAC, respectively.

(2)

Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.

TI strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing, vias/backdrill,

PCB material, etc.) in order to achieve the full specified clock frequency. Refer to the Jacinto 7 DDR Board Design and Layout

Guidelines for details.

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

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