TDA4VE...ALZQ1 datasheet(190/251 Pages) TI

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RESETn

HYPERBUS_TIMING_03

CSn

Figure 7-68. HyperBus Timing Diagrams – Reset

For more information, see HyperBus Interface section in Peripherals chapter in the device TRM.

7.10.5.12 I2C

The device contains several multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was

designed to be compliant to the Philips I2C-bus™ specification version 2.1. However, the device IO Buffers are

not fully compliant to the I2C electrical specification. Some I2C instances use the LVCMOS Buffer Type, while

other instances use the I2S OD FS Buffer type. See the Pin Attributes table to determine the IO Buffer

Type used for each I2C instance on this device. The I2C speeds supported and exceptions are described per

IO Buffer Type below:

• I2C instances that use the LVCMOS buffer type

– Speeds:

• Standard-mode (up to 100 Kbits/s)

– 1.8 V

– 3.3 V

• Fast-mode (up to 400 Kbits/s)

– 1.8 V

– 3.3 V

– Exceptions:

• The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C

specification because they are implemented with higher performance LVCMOS push-pull IOs that were

designed to support other signal functions that could not be implemented with I2C compatible IOs. The

LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This

emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z

state.

• The I2C specification defines a maximum input voltage VIH of (VDD

max + 0.5 V), which exceeds the

absolute maximum ratings for the device IOs. The system must be designed to ensure the I2C signals

never exceed the limits defined in the Absolute Maximum Ratings section of this data sheet.

• I2C instances that use the I2C OD FS buffer type

– Speeds:

• Standard-mode (up to 100 Kbits/s)

– 1.8 V

– 3.3 V

• Fast-mode (up to 400 Kbits/s)

– 1.8 V

– 3.3 V

• Hs-mode (up to 3.4 Mbit/s)

– 1.8 V

– Exceptions:

• The IOs associated with these ports were not design to support Hs-mode while operating at 3.3 V. So

Hs-mode is limited to 1.8-V operation.

• The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.8

V/ns (or 8E+7 V/s). This limit is more restrictive than the minimum fall time limits defined in the I2C

specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow

the rise and fall times such that they do not exceed a slew rate of 0.8 V/ns.

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

190

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