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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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KSZ9567RTXI Scheda tecnica(PDF) 137 Page - Microchip Technology |
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KSZ9567RTXI Scheda tecnica(HTML) 137 Page - Microchip Technology |
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137 / 232 page  2017-2019 Microchip Technology Inc. DS00002329D-page 137 KSZ9567R 5.2.1.7 Port Operation Control 0 Register 0 ACL Interrupt Enable Applies to all ports. 0 = Interrupt enabled 1 = Interrupt disabled R/W 0b Address: 0xN020 Port N: 1-7 Size: 8 bits Bits Description Type Default 7 Local MAC Loopback Data going from the internal switch fabric to an egress port is looped back in the MAC of that egress port and returned to the internal switch fabric. 1 = Local MAC loopback 0 = Normal operation R/W 0b 6 Remote MAC Loopback Data received at the external pins of a port is looped back in the MAC of that port and sent out the same port, without passing through the internal switch fabric. For PHY ports, data is received on the RX+/- pins and transmitted out the TX+/- pins. For xMII ports, data is received on the TXD pins and transmitted on the RXD pins. This loopback path does not include an RX-to-TX elastic buffer. Use small packet sizes and only one or two packets at a time to avoid data corruption. 1 = Remote MAC loopback 0 = Normal operation R/W 0b 5:3 RESERVED RO 000b 2 Tail Tag Enable When tail tagging is enabled for a port, it designates that port to be the “host” or “CPU” port. Do not enable tail tagging for more than one port. See the tail tagging description for details. 1 = Enable tail tagging on this port 0 = Disable tail tagging for this port R/W 0b 1:0 Egress Queue Split Enable 11 = Reserved 10 = Four egress queues. Packets are assigned to a queue based on priority. 01 = Two egress queues. Packets are assigned to a queue based on priority. 00 = Single egress queue. There is no priority differentiation. R/W 00b Bits Description Type Default |
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