UPSD3422EB40U6 datasheet(101/300 Pages) STMICROELECTRONICS

101 / 300 page

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

Standard 8032 timer/counters

101/300

20.6.1

Capture mode

In Capture mode there are two options which are selected by the bit EXEN2 in T2CON.

Figure 27 on page 105 illustrates Capture mode.

If EXEN2 = 0, then Timer 2 is a 16-bit timer if C/T2 = 0, or it is a 16-bit counter if C/T2 = 1,

either of which sets the interrupt flag bit TF2 upon overflow.

If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0

transition at external input pin T2X causes the current value in the Timer 2 registers, TL2

and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the

transition at T2X causes interrupt flag bit EXF2 in T2CON to be set. Either flag TF2 or EXF2

will generate an interrupt and the MCU must read both flags to determine the cause. Flags

TF2 and EXF2 are not automatically cleared by hardware, so the firmware servicing the

interrupt must clear the flag(s) upon exit of the interrupt service routine.

20.6.2

Auto-reload mode

In the Auto-reload mode, there are again two options, which are selected by the bit EXEN2

in T2CON. Figure 28 on page 106 shows Auto-reload mode.

If EXEN2 = 0, then when Timer 2 counts up and rolls over from FFFFh it not only sets the

interrupt flag TF2, but also causes the Timer 2 registers to be reloaded with the 16-bit value

contained in registers RCAP2L and RCAP2H, which are preset with firmware.

If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0

transition at external input T2X will also trigger the 16-bit reload and set the interrupt flag

EXF2. Again, firmware servicing the interrupt must read both TF2 and EXF2 to determine

the cause, and clear the flag(s) upon exit.

Note:

The UPSD34xx does not support selectable up/down counting in Auto-reload mode (this

feature was an extension to the original 8032 architecture).

Table 60.

T2CON: Timer 2 control register (SFR C8h, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

Table 61.

T2CON register bit definition

Bit

Symbol

R/W

Definition

7TF2

R,W

Timer 2 flag, causes interrupt if enabled.

TF2 is set by hardware upon overflow. Must be cleared by

firmware. TF2 will not be set when either RCLK or TCLK =1.

EXF2

R,W

Timer 2 flag, causes interrupt if enabled.

EXF2 is set when a capture or reload is caused by a negative

transition on T2X pin and EXEN2 = 1. EXF2 must be cleared

by firmware.

RCLK(1)

R,W

UART0 Receive Clock control.

When RCLK = 1, UART0 uses Timer 2 overflow pulses for its

receive clock in Modes 1 and 3. RCLK=0, Timer 1 overflow is

used for its receive clock

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