S71GS256 datasheet(113/195 Pages) SPANSION

113 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

113

Ad vance

Info rmat i o n

LB#/UB# Operation

The LB# enable and UB# enable signals support byte-wide data transfers. During

READ operations, the enabled byte(s) are driven onto the DQs. The DQs associ-

ated with a disabled byte are put into a High-Z state during a READ operation.

During WRITE operations, any disabled bytes will not be transferred to the RAM

array and the internal value will remain unchanged. During an asynchronous

WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#,

LB#, or UB#, whichever occurs first.

When both the LB# and UB# are disabled (HIGH) during an operation, the device

will disable the data bus from receiving or transmitting data. Although the device

will seem to be deselected, it remains in an active mode as long as CE# remains

LOW.

Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.

Figure 29. Refresh Collision During READ Operation

Additional WAIT states inserted to allow refresh completion.

CLK

A[22:0]

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

LB#/UB#

Don't care

Undefined

Legend:

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

High-Z

VOH

VOL

D[0]

D[1]

D[2]

D[3]

VOH

VOL

Address

Valid

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