ADE7169ASTF16 datasheet(109/140 Pages) AD

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Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 109 of 140

PLL

The ADE7169F16 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable

4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving when

maximum core performance is not required. The default core clock is the PLL clock divided by 4 or 1.024 MHz. The ADE energy

measurement clock is derived from the PLL clock and is maintained at 4.096/5 MHz, 819.2 kHz across all CD settings. The PLL is

controlled by the CD[2:0] bits in the Power Control SFR (POWCON, 0xC5). To protect erroneous changes to the Power Control SFR

(POWCON, 0xC5), a key is required to modify the register. First the POWCON Key SFR (KYREG, 0xC1) is written with the key, 0xA7,

and then a new value is written to the Power Control SFR (POWCON, 0xC5).

If the PLL loses lock, the MCU is reset and the PLLFAULT bit is set in the Peripheral Configuration SFR (PERIPH, 0xF4). Set the

PLL_FLT_ACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the PLL fault, clearing the PLLFAULT flag.

PLL SFR REGISTER LIST

Power Control SFR (POWCON, 0xC5)

Bit

Location

Bit

Mnemonic

Default

Value

Description

7-5

RESERVED

COREOFF

Set this bit to shut down the core if in the PSM1 operating mode.

RESERVED

Controls the core clock frequency, Fcore. Fcore=4.096MHz/2CD

CD[2:0]

Fcore (MHz)

4.096

2.048

1.024

0.512

0.256

0.128

0.064

2-0

CD[2:0]

010

0.032

Table 106. POWCON Key SFR (KYREG, 0xC1)

Bit

Location

Bit

Mnemonic

Default

Value

Description

7-0

KYREG

Write 0xA7 to the KYREG SFR before writing the POWCON SFR, to unlock it.

Peripheral Configuration SFR (PERIPH, 0xF4)

Bit

Location

Bit

Mnemonic

Default

Value

Description

RXFLAG

If set, indicates that a RX Edge event triggered wakeup from PSM2

Indicates the power supply that is connected internally to VSW.

0 VSW=VBAT

VSWSOURCE

1 VSW=VDD

VDD_OK

If set, indicates that VDD power supply is ok for operation

PLL_FLT

If set, indicates that PLL is not locked

RESERVED

EXTREFEN

Set this bit if an external reference is connected to the REFIN pin.

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