MC68340 datasheet(274/441 Pages) FREESCALE

274 / 441 page

6- 24

MC68340 USER’S MANUAL

MOTOROLA

MCR1, MCR2

$780, $7A0

9876543210

STP

FRZ1

FRZ0

ISM

SUPV

MAID

IARB

RESET:

0000000010000000

Supervisor Only

STP—Stop Bit

1 = Setting the STP bit stops all clocks within the DMA module except for the clock

from the IMB. The clock from the IMB remains active to allow the CPU32 access

to the MCR. The clock stops on the low phase of the clock and remains stopped

until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to DMA

module registers while in stop mode produce a bus error. The DMA module

should be disabled in a known state before setting the STP bit. The STP bit

should be set prior to executing the LPSTOP instruction to reduce overall power

consumption.

0 = The channel operates in normal mode.

NOTE

The DMA module uses only one STP bit for both channels. A

read or write to either MCR accesses the same STP control bit.

FRZ1, FRZ0—Freeze

These bits determine the action taken when the FREEZE signal is asserted on the IMB

when the CPU32 has entered background debug mode. The DMA module negates

and keeps it negated until FREEZE is negated or reset. Table 6-1 lists the action taken

for each bit combination.

Table 6-1. FRZx Control Bits

FRZ1

FRZ0

Action

Ignore FREEZE

Reserved

Freeze on Boundary*

Reserved

*The boundary is defined as any bus cycle by

the DMA module.

NOTE

The DMA module uses only one set of FRZx bits for both

channels. A read or write to either MCR accesses the same

FRZx control bits.

Freescale Semiconductor, Inc.

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