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MC68340 Scheda tecnica(PDF) 115 Page - Freescale Semiconductor, Inc |
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MC68340 Scheda tecnica(HTML) 115 Page - Freescale Semiconductor, Inc |
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115 / 441 page  4- 18 MC68340 USER’S MANUAL MOTOROLA the MCR disables the software watchdog and periodic interrupt timer, and setting the FRZ0 bit in the MCR disables the bus monitor. 4.3 PROGRAMMING MODEL Figure 4-8 is a programming model (register map) of all registers in the SIM40. For more information about a particular register, refer to the description of the module or function indicated in the right column. The ADDR (address) column indicates the offset of the register from the address stored in the module base address register. The FC (function code) column indicates whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user space (S/U). For the registers discussed in the following pages, the number in the upper right-hand corner indicates the offset of the register from the address stored in the module base address register. The numbers on the top line of the register represent the bit position in the register. The second line contains the mnemonic for the bit. The numbers below the register represent the bit values after a hardware reset. The access privilege is indicated in the lower right-hand corner. NOTE: A CPU32 RESET instruction will not affect any of the SIM40 registers. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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