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SPSB100 Scheda tecnica(PDF) 141 Page - STMicroelectronics |
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SPSB100 Scheda tecnica(HTML) 141 Page - STMicroelectronics |
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141 / 214 page  Bit Name Description 011: Step 3 100: Step 4 101: Step 5 110: Step 6 111: Step 7 12 BUCK3_PD_STEP_OFF_2 To define BUCK3 turn-off steps 000: Step 1 001: Step 2 010: Step 3 011: Step 4 100: Step 5 101: Step 6 11X: Step 7 11 BUCK3_PD_STEP_OFF_1 10 BUCK3_PD_STEP_OFF_0 9 BUCK3_IPEAK_1 BUCK3 peak switching current 00: 4.0 A 01: 5.0 A 10: 6.0 A 11: 7.2 A 8 BUCK3_IPEAK_0 Table 123. DCR12 (0x0C) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - (R) - (R) - (R) - (R) - (R) - (R) - (R) - (R) BUCK3_REGFAIL_GO_REC BUCK3_SS_VALUE_1 BUCK3_SS_VALUE_0 BUCK3_REFRESH_FREQ CRC3 CRC2 CRC1 CRC0 BUCK3 regulator fail go receiver bit BUCK3 soft start value bit 1 BUCK3 soft start value bit 0 BUCK3 refresh frequency bit Cyclic redundancy checking bit 3 Cyclic redundancy checking bit 2 Cyclic redundancy checking bit 1 Cyclic redundancy checking bit 0 Table 124. DCR12 (0x0C) LSB description Bit Name Description 7 BUCK3_REGFAIL_GO_REC 1: A fail on BUCK3 regulator initiates a power-down sequence and moves the state machine to REC-2 state 0: A fail on BUCK3 regulator sends an IRQ (UV, OV, PG_nok, TW are maskable by SPI, but not TSD), and turns the regulator OFF if the fail is unmasked (UV, PG_nok are maskable by SPI, but not OV and TSD. TW never turns the regulator OFF) 6 BUCK3_SS_VALUE_1 BUCK3 soft start setting 00: 8.V/ms 01: 4.3 V/ms 10: 1.7 V/ms 11: 0.8 V/ms 5 BUCK3_SS_VALUE_0 4 BUCK3_REFRESH_FREQ 1: Refresh frequency 1 kHz 0: Refresh frequency 25 kHz 3 CRC 3 SPSB100 SPI registers DS14640 - Rev 1 page 141/214 |
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