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ST7LITE49M Scheda tecnica(PDF) 150 Page - STMicroelectronics

Il numero della parte ST7LITE49M
Spiegazioni elettronici  8-bit MCU with single voltage Flash memory data EEPROM, ADC, 8/12-bit timers, and I²C interface
PDF  188 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7LITE49M Scheda tecnica(HTML) 150 Page - STMicroelectronics

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Electrical characteristics
ST7LITE49M
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13.4
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for Halt mode
for which the clock is stopped).
13.4.1
Supply current
TA = -40 to +125 °C unless otherwise specified.
Table 74.
Supply current characteristics
Symbol
Parameter
Conditions
Typ
Max
Unit
IDD
Supply current in Run mode(1)
fCPU = 4 MHz
2.5
4.5(2)
mA
fCPU = 8 MHz
5.0
9(2)
Supply current in Wait mode(3)
fCPU = 4 MHz
1.1
2(2)
fCPU = 8 MHz
2
3.5(2)
Supply current in Slow mode(4)
fCPU/32 = 250 kHz
550
900
µA
Supply current in Slow-Wait mode(5)
fCPU/32 = 250 kHz
450
750
Supply current in AWUFH mode(6)(7)
50
90(2)
Supply current in Active Halt mode
120
200
Supply current in Halt mode(8)
TA=85°C
0.5
5
TA=125°C
Supply current in Run mode(1)
fCPU = 4 MHz
1.4
2.5(2)
mA
Supply current in Wait mode(3)
fCPU = 4 MHz
600
900(2)
Supply current in Slow mode(4)
fCPU/32 = 250 kHz
300
500(2)
µA
Supply current in Slow-Wait mode(5)
fCPU/32 = 250 kHz
250
450(2)
Supply current in AWUFH mode(6)(7)
20
40(2)
Supply current in Active Halt mode
80
120(2)
Supply current in Halt mode(8)
TA=85°C
0.5
5(2)
TA=125°C
1.
CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in
reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2.
Data based on characterization, not tested in production.
3.
All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
4.
Slow mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no
load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
5.
Slow-Wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
6.
All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU max.
7.
This consumption refers to the Halt period only and not the associated run period which is software dependent.
8.
All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.



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