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PM7367 Scheda tecnica(PDF) 116 Page - PMC-Sierra, Inc |
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PM7367 Scheda tecnica(HTML) 116 Page - PMC-Sierra, Inc |
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116 / 323 page ![]() PM7367 FREEDM-32P32 DATA SHEET PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 102 Register 0x024 : FREEDM-32P32 Master Performance Monitor Control Bit Type Function Default Bit 31 to Bit 16 Unused XXXXH Bit 15 Unused X Bit 14 R/W TP2EN 0 Bit 13 R/W TABRT2EN 0 Bit 12 R/W RP2EN 0 Bit 11 R/W RLENE2EN 0 Bit 10 R/W RABRT2EN 0 Bit 9 R/W RFCSE2EN 0 Bit 8 R/W RSPE2EN 0 Bit 7 Unused X Bit 6 R/W TP1EN 0 Bit 5 R/W TABRT1EN 0 Bit 4 R/W RP1EN 0 Bit 3 R/W RLENE1EN 0 Bit 2 R/W RABRT1EN 0 Bit 1 R/W RFCSE1EN 0 Bit 0 R/W RSPE1EN 0 This register configures the events that are accumulated in the two configurable performance monitor counters in the PMON block. Note This register is not byte addressable. Writing to this register modifies all the bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to this register. |
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