KK74ACT373DW datasheet(4/6 Pages) KODENSHI

Il numero della parte	KK74ACT373DW

Spiegazioni elettronici	Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

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Produttore elettronici	KODENSHI [KODENSHI_AUK CORP.]

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KK74ACT373

AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

25

°C

-40

°C to 85°C

Unit

Min

Max

Min

Max

tPLH

Propagation Delay, Input D to Q (Figure 1)

2.5

10

1.5

11.5

ns

tPHL

Propagation Delay, Input D to Q (Figure 1)

2.0

10

1.5

11.5

ns

tPLH

Propagation Delay, Latch Enable to Q (Figure 2)

2.5

11

2.0

11.5

ns

tPHL

Propagation Delay, Latch Enable to Q (Figure 2)

2.0

10

1.5

11.5

ns

tPZH

Propagation Delay, Output Enable to Q

(Figure 3)

2.0

9.5

1.5

10.5

ns

tPZL

Propagation Delay, Output Enable to Q

(Figure 3)

2.0

9.0

1.5

10.5

ns

tPHZ

Propagation Delay, Output Enable to Q

(Figure 3)

2.5

11

2.5

12.5

ns

tPLZ

Propagation Delay, Output Enable to Q

(Figure 3)

1.5

8.5

1.0

10

ns

CIN

Maximum Input Capacitance

4.5

pF

Typical @25

°C,V

CC=5.0 V

CPD

Power Dissipation Capacitance

40

pF

TIMING REQUIREMENTS (VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

25

°C

-40

°C to 85°C

Unit

tsu

Minimum Setup Time, Input D to Latch Enable

(Figure 4)

7.0

8.0

ns

th

Minimum Hold Time, Latch Enable to

Input D (Figure 4)

0

1.0

ns

tw

Minimum Pulse Width, Latch Enable

(Figure 2)

2.0

8.0

ns

4

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KK74ACT373DW Scheda tecnica(PDF) 4 Page - KODENSHI_AUK CORP.

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