MPC8280 datasheet(318/1386 Pages) FREESCALE

318 / 1386 page

PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

9-10

Freescale Semiconductor

A read transaction starts when FRAME is asserted for the first time and the PCI_C/BE[3-0] signals

indicate a read command. Figure 9-3 shows an example of a single beat read transaction.

Figure 9-3. Single Beat Read Example

Figure 9-4 shows an example of a burst read transaction.

Figure 9-4. Burst Read Example

During the turnaround-cycle following the address phase, the PCI_C/BE[3-0] signals indicate which byte

lanes are involved in the data phase. The turnaround-cycle must be enforced by the target with the TRDY

signal if using fast DEVSEL assertion. The earliest the target can provide valid data is one cycle after the

turnaround-cycle. The target must drive the AD[31-0] signals when DEVSEL is asserted.

The data phase completes when data is transferred, which occurs when both IRDY and TRDY are asserted

on the same clock edge. When either is negated a wait cycle is inserted and no data is transferred. To

indicate the last data phase IRDY must be asserted when FRAME is negated.

A write transaction starts when FRAME is asserted for the first time and the PCI_C/BE[3-0] signals

indicate a write command. Figure 9-5 shows an example of a single beat write transaction.

ADDR

CMD

BYTE ENABLES

PCI_CLK

AD[31:0]

PCI_C/BE[3:0]

FRAME

IRDY

DEVSEL

TRDY

DATA

ADDR

CMD

PCI_CLK

AD[31:0]

PCI_C/BE[3:0]

FRAME

IRDY

DEVSEL

TRDY

DATA2

DATA1

BYTE ENABLES 2

BYTE ENABLES 1

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