MPC8280 datasheet(351/1386 Pages) FREESCALE

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PCI Bridge

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

9-43

in a PIBARx register causes a change in the GPLABARx in the base address bits that are non-masked by

PICMRx, and vice versa.

The system host is responsible for the configuration of the base address by writing to GPLABARx;

therefore, in PCI agent mode, the PIBARx registers should be read-only. However, if the PCI bridge is

defined as the PCI host, it may be easier to configure its own inbound base address by writing directly to

the PIBARx registers.

Figure 9-30. PCI Inbound Base Address Registers (PIBAR

Table 9-17 describes PIBARx.

9.11.1.17 PCI Inbound Comparison Mask Registers (PICMR

The PCI inbound comparison mask registers (PICMRx), shown in Figure 9-31, defines the inbound

window’s size. In PCI agent mode, this register should be initialized (either by the core or by the CP’s

automatic EPROM load) before the AGENT_CFG_LOCK bit (see Section 9.11.2.22, “PCI Bus Function

tied to the GPLABARx registers; see Section 9.11.2.14, “General Purpose Local Access Base Address

Registers (GPLABARx).”

Field

—

Reset

0000_0000_0000_0000

R/W

Addr

0x108F2 (PITAR0); 0x108DA (PITAR0)

Field

Reset

0000_0000_0000_0000

R/W

Addr

0x108F0 (PITAR0); 0x108D8 (PITAR0)

Table 9-17. PIBAR

x Field Descriptions

Bits

Name

Description

31–20

—

Reserved, should be cleared.

19–0

Base address. PCI address which is the starting point for the inbound translation

window.This corresponds to bits 31–12 of a 32-bit address.

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