MPC8280 datasheet(417/1386 Pages) FREESCALE

417 / 1386 page

Clocks and Power Control

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

10-7

Note: At both Agent and Host PCI modes, when PCI_MODCK = 0, the ratio of CPM_CLK/PCI_CLK should be calculated from

PCIDF as follows:

CPM_CLK / PCI_CLK = (PCIDF + 1) / 2.

At both Agent and Host PCI modes, when PCI_MODCK = 1, the ratio of CPM_CLK/PCI_CLK should be calculated from

PCIDF as follows:

PCIDF = 3 > CPM_CLK / PCI_CLK = 4

PCIDF = 5 > CPM_CLK / PCI_CLK = 6

PCIDF = 7 > CPM_CLK / PCI_CLK = 8

PCIDF = 9 > CPM_CLK / PCI_CLK = 5

PCIDF = B > CPM_CLK / PCI_CLK = 6

10.5

System Clock Mode Register (SCMR)

The PLL, low power, and reset control register (SCMR), shown in Figure 10-6, hold the parameters

necessary for determining the output clock frequencies. To understand how the interaction of these values,

refer to Section 10.1, “MPC8280 Clock Block Diagram.”

Table 10-3 describes SCMR fields.

Field PLLBP

—

CORECNF

BUSDF

CPMDF

Reset

—

Refer to Table 10-3

R/W

Addr

0x10C88

Field

—

PLLMF

Reset

0000_0000_0000

Refer to Table 10-3

R/W

Addr

0x10C8A

Figure 10-6. System Clock Mode Register (SCMR)

Table 10-3. SCMR Field Descriptions

Bits

Name

Defaults

Description

PORESET

Hard Reset

PLLBP

Config pin1

Unaffected

Reset configuration for PLL bypass.

0 Normal operation

1 Bypass CPM PLL

1–2

—

Reserved

3–7

CORECNF

Config pins

Unaffected

Core PLL configuration. Refer to Table 10-4 to see how these bits

translate to the actual core PLL multiplication mode.

8–11

BUSDF

Config pins

Unaffected

60x bus division factor.

12–15

CPMDF

Config pins

Unaffected

CPM division factor. This value is always 1.

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