MPC8280 datasheet(612/1386 Pages) FREESCALE

612 / 1386 page

Serial Interface with Time-Slot Assigner

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

15-34

Freescale Semiconductor

4. CMXSCR = 0xC040_0000. SCC2 and SCC1 are connected to the TSA. SCC1 supports the grant

mechanism since it is on the D channel.

5. CMXSI1CR = 0x00. TDMa uses CLK1.

6. Set PPARA[6–9]. Configures L1TXDa[0], L1RXDa[0], L1TSYNCa and L1RSYNCa.

7. Set PSORA[6–9]. Configures L1TXDa[0], L1RXDa[0], L1TSYNCa and L1RSYNCa.

8. Set PDIRA[9]. Configures L1TXDa[0].

9. Set PODRA[9]. Configures L1TXDa[0] to an open-drain output.

10. Set PPARC[30,31]. Configures L1TCLKa and L1RCLKa.

11. Clear PDIRC[30,31]. Configures L1TCLKa and L1RCLKa.

12. Clear PSORC[30,31]. Configures L1TCLKa and L1RCLKa.

13. Set PPARB[17]. Configures L1CLKO and L1RQa.

14. Clear PSORB[17]. Configures L1CLKO and L1RQa.

15. Set PDIRB[17]. Configures L1CLKO and L1RQa.

16. If the 1x GCI data clock is required, set PBPAR bit 16 and PBDIR bit 16 and clear PSORB 16,

which configures L1CLKOa as an output.

17. Configure SCC1 for HDLC operation (to handle the LAPD protocol of the D channel). Configure

SMC1 for SCIT operation and configure SCC2 and SMC2 as preferred.

18. SI1GMR = 0x11. Enable TDMa (one static TDM), STZ for TDMa.

19. SI1CMDR is not used.

20. SI1STR does not need to be read.

21. Enable the SCC1, SCC2, SMC1 and SMC2.

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