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MPC8280 Scheda tecnica(PDF) 893 Page - Freescale Semiconductor, Inc

Il numero della parte MPC8280
Spiegazioni elettronici  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Produttore elettronici  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Scheda tecnica(HTML) 893 Page - Freescale Semiconductor, Inc

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Multi-Channel Controllers (MCCs)
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
29-3
•
Channel extra parameters. Each channel use 8 bytes of extra parameters placed in the DPRAM at
offset XTRABASE + 8*CH_NUM (relative to the DPRAM base address). XTRABASE is one of
the global MCC parameters. Refer to Section 29.4, “Channel Extra Parameters.” Note that the
DPRAM memory corresponding to the inactive channels can be used for other purposes.
•
Superchannel table (used only if superchannelled timeslots are defined in SIRAM programming).
This table is placed in the DPRAM from the offset SCTPBASE (relative to the DPRAM base
address). SCTPBASE is one of the global MCC parameters. The super channel table is described
in Section 29.5.1, “Superchannel Table.”
•
BD tables placed in the external memory. All the BD tables associated with one MCC must reside
in a 512-KByte segment. The absolute base addresses of a channel BD table is MCCBASE +
8*RBASE (for the receiver) and MCCBASE + 8*TBASE (for the transmitter). MCCBASE is one
of the global MCC parameters and RBASE/TBASE are channel extra parameters. Each BD table
is a circular queue. One BD includes status bits, start address and length of a data buffer.
Figure 29-1 shows the BD structure for one MCC.
•
Circular interrupt tables placed in the external memory. There is one table for the transmitter
interrupts (base address TINTBASE) and between one and four tables for receiver interrupts (base
address RINTBASE0–RINTBASE4). TINTBASE and RINTBASE0–RINTBASE4 are global
MCC parameters.
•
Three registers (MCCE, MCCM, and MCCF) at described in Section 29.8.1, “MCC Event Register
(MCCE)/Mask Register (MCCM),” and Section 29.6, “MCC Configuration Registers (MCCFx).”
Figure 29-1. BD Structure for One MCC
Channel j TxBD
Table
Channel 0 Parameter
Channel 1 Parameter
Channel j Extra
RBASE
TBASE
Global MCC
MCCBASE
DPRAM
Buffer Descriptor
+
+
Channel j RxBD
Table
External Memory
512 Kbytes
x8
x8
DPRAM_base
Table Base Address
Parameter
Parameters



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