MPC8280 datasheet(938/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-48

Freescale Semiconductor

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A time slot that was previously used by a single channel and had a width different from 8 bits

cannot be added dynamically to a super channel.

29.11 MCC Latency and Performance

The CPM moves data between an MCC channel's FIFOs and temporary 8 byte data buffers in the

corresponding channel-specific parameter RAM. RX FIFOs provide data to the ZDSTATE fields and TX

FIFOs are fed from the ZISTATE fields. This traffic is considered completely internal to the CPM.

In addition to the loading and storing of buffer descriptors, the CPM transfers data for an MCC channel

to/from external memory 8 bytes at a time, to replenish or empty the ZISTATE and ZDSTATE fields as

appropriate. The user may then estimate how frequently the MCC will need to transfer data on an external

bus for a particular channel by calculating how quickly 8 bytes will be sent or received on that channel.

If multiple synchronized TDMs are used (as an example 8 T1 with common clock/sync) it is recommended

to start the TDMs out of phase relative to each other, in order to spread out CPM and bus utilization. This

avoids CPM and bus activity peaks when all the channels would require CPM attention and possibly have

to transfer data to/from the memory simultaneously.

When MCC FIFO activity starts, the MCC begins to consume CPM bandwidth immediately upon enabling

a TDM which has MCC-related SIRAM programming. This is regardless of whether a channel is stopped

or has the “start condition” programmed in the RSTATE and TSTATE channel-specific parameters. If a

user wishes to spread out CPM and bus utilization for the MCC channels on a particular TDM, those

channels must be dynamically added to the SIRAM programming in an evenly distributed fashion over

multiple TDM frames.

MPC8280 Scheda tecnica(PDF) 938 Page - Freescale Semiconductor, Inc