MPC8280 datasheet(1145/1386 Pages) FREESCALE

1145 / 1386 page

ATM AAL2

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

33-39

An interrupt entry for the VC is shown in Figure 33-24.

Table 33-15 describes the interrupt queue entry fields for the VC. All the receive error events are enabled

by setting RCT[EM].

Offset + 0x00

—

0000_0000

Error_Code

Offset + 0x02

Channel Code (CC)

Figure 33-24. AAL2 Interrupt Queue Entry CID = 0

Table 33-15. AAL2 Interrupt Queue Entry CID = 0 Field Descriptions

Offset

Bits

Name

Description

0x00

Valid interrupt entry

0 This interrupt queue entry is free and can be used by the CP.

1 This interrupt queue entry is valid. The host should read this interrupt and clear this

bit.

1—

—

Wrap bit. When set, this is the last interrupt circular table entry. During initialization,

the host must clear all W bits in the table except the last one, which must be set.

3–10

CID

CID number. Equals zero. This exception applies to the whole cell.

—

Reserved

12–15

Error_Code

A receive error was detected.

0000 Parity error of the OSF.

0001 The STF sequence number is incorrect.

0010 The number of octets expected to overlap into this cell does not match the OSF.

0011 OSF is greater than 47.

0100 A packet HEC error was detected.

0101 The length of the CPS packet exceeds the Max_SDU_Length.

0111 A packet HEC error was detected in a split header packet.

0x02

—

Channel code specifies the ATM channel number associated with this interrupt.

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