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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

2-1

Chapter 2

G2_LE Core

The MPC8280 contains an embedded G2_LE processor core, which is a derivative of the G2 core and the

original MPC603e PowerPC microprocessor design. This chapter provides an overview of the basic

functionality of the G2_LE processor core. For detailed information regarding the processor, refer to the

following:

•

G2 PowerPC Core Reference Manual

•

The Programming Environments for 32-Bit Implementations of the PowerPC Architecture

This section describes the details of the processor core, provides a block diagram showing the major

functional units, and briefly describes how those units interact.

MPC8280-specific implementation includes most of the G2_LE features. The unimplemented features are

described in the Section 2.2, “G2_LE Core Features.”

The signals associated with the processor core are described individually in Chapter 7, “60x Signals.”

Chapter 8, “The 60x Bus,” describes how those signals interact.

2.1

Overview

The processor core is a low-power implementation of the family reduced instruction set computing (RISC)

microprocessors that implement the PowerPC architecture. The processor core implements the 32-bit

portion of the PowerPC architecture, which supports 32-bit effective addresses, integer data types of 8, 16,

and 32 bits, and floating-point data types of 32 and 64 bits.

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