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MPC8280 Scheda tecnica(PDF) 1277 Page - Freescale Semiconductor, Inc

Il numero della parte MPC8280
Spiegazioni elettronici  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Produttore elettronici  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Scheda tecnica(HTML) 1277 Page - Freescale Semiconductor, Inc

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FCC HDLC Controller
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
37-15
Table 37-9 describes FCCE/FCCM fields.
Figure 37-8 shows interrupts that can be generated in the HDLC protocol.
Table 37-9. FCCE/FCCM Field Descriptions
Bits
Name
Description
0–7
—
Reserved, should be cleared.
8
GRA
Graceful stop complete. A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT
command, is now complete. GRA is set as soon as the transmitter finishes transmitting any frame
that is in progress when the command was issued. It is set immediately if no frame is in progress
when the command is issued.
9–10
—
Reserved, should be cleared.
11
TXE
Tx error. An error (CTS lost or underrun) occurs on the transmitter channel. This event is not
maskable via the TxBD[I] bit.
12
RXF
Rx frame. A complete frame is received on the HDLC channel. This bit is set no sooner than two
clocks after receipt of the last bit of the closing flag.
13
BSY
Busy condition. A frame is received and discarded due to a lack of buffers.
14
TXB
Transmit buffer. Enabled by setting TxBD[I]. A buffer is sent on the HDLC channel. TXB is set no
sooner than when the last bit of the closing flag begins its transmission if the buffer is the last one
in the frame. Otherwise, TXB is set after the last byte of the buffer is written to the transmit FIFO
buffer.
15
RXB
Receive buffer. When RXB = 1, a buffer for which the I bit is set in the corresponding BD was filled,
regardless if the end of a frame was completed in it.
16–21
—
Reserved, should be cleared.
22
FLG
Flag status changed. The HDLC controller stops or starts receiving HDLC flags. The real-time status
can be obtained in FCCS; see Section 37.10, “FCC Status Register (FCCS).”
23
IDL
Idle sequence status changed. A change in the status of the serial line is detected on the HDLC line.
The real-time status can be read in FCCS; see Section 37.10, “FCC Status Register (FCCS).”
24–31
—
Reserved, should be cleared.



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