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STM32H563RG Scheda tecnica(PDF) 183 Page - STMicroelectronics

Il numero della parte STM32H563RG
Spiegazioni elettronici  Arm® Cortex®-M33 32-bit MCU TrustZone® FPU, 375 DMIPS, 250 MHz, 2-Mbyte flash, 640-Kbyte RAM, math accelerators
PDF  270 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H563RG Scheda tecnica(HTML) 183 Page - STMicroelectronics

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DS14258 Rev 5
183/270
STM32H562xx and STM32H563xx
Electrical characteristics
238
Synchronous waveforms and timings
Figures 37 through 40 represent synchronous waveforms, tables 78 through 81 provide the
corresponding timings. The results shown in these tables are obtained with the following
FMC configuration:
•
BurstAccessMode = FMC_BurstAccessMode_Enable
•
MemoryType = FMC_MemoryType_CRAM
•
WriteBurst = FMC_WriteBurst_Enable
•
CLKDivision = 1
•
DataLatency = 1 for NOR flash, DataLatency = 0 for PSRAM.
•
With capacity load CL = 30 pF
In all the timing tables, Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK
maximum values:
•
For 2.7 V < VDD < 3.6 V: maximum FMC_CLK = 100 MHz at CL = 20 pF
•
For 1.71 V < VDD < 1.8 V: maximum FMC_CLK = 95 MHz at CL = 20 pF
•
For 1.71 V < VDD < 1.8 V: maximum FMC_CLK = 100 MHz at CL = 15 pF
Figure 37. Synchronous multiplexed NOR/PSRAM read timings
FMC_CLK
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NOE
FMC_AD[15:0]
AD[15:0]
D1
D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tw(CLK)
tw(CLK)
Data latency = 0
BUSTURN = 0
td(CLKL-NExL)
td(CLKH-NExH)
t d(CLKL-NADVL)
td(CLKL-AV)
td(CLKL-NADVH)
td(CLKH-AIV)
td(CLKL-NOEL)
td(CLKH-NOEH)
td(CLKL-ADV)
td(CLKL-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(ADV-CLKH)
th(CLKH-ADV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
tsu(NWAITV-CLKH)
th(CLKH-NWAITV)
MS32757V1



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