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TMPR3916 Scheda tecnica(PDF) 162 Page - Toshiba Semiconductor |
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TMPR3916 Scheda tecnica(HTML) 162 Page - Toshiba Semiconductor |
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162 / 225 page ![]() Chapter 9 Synchronous Serial I/O (TXSEI) Preliminary 9-7 SEI Control Register 1 (SECR1) The number of bits per frame is configured using this register. This register could only be written, when the module is in configuration mode. Bit 3130 292827 262524 Name Bit 2322 212019 181716 Name Bit 1514 131211 10 9 8 Name SER Bit 7 6 543 210 Name SSZ Bit Name Function Reset Value R/W 31:16 Unused 0x0000 R 15:8 SER In master-mode, this setting controls the bit-rate for transmission. The internal clock rate generator is implemented as a down counter. The SER setting specifies the reload value for this counter. 0x01 R/W 7:5 wired to zero 0R 4:0 SSZ Transfer Size 0x05 = 5 bits 0x06 = 6 bits ... ... 0x10 = 16 bits others = invalid setting Note: If SSZ has an invalid setting, the TXSEI will not work properly. 0 R/W This register can only be written, if TXSEI is in configuration mode. The clock-rate on the SEI bus can be calculated using the following formula: 1) ( 2 + ⋅ = SER f f system SEI |
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