TMP93CS44 datasheet(160/224 Pages) TOSHIBA

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TMP93CS44/S45

2004-02-10

93CS44-158

3.10.5

Data Transfer in I

2C Bus Mode

(1) Device initialization

First, set SBICR1<ACK, SCK2:0>. Specify 0 to bits 7 to 5 and 3 in the SBICR1.

Set the slave address <SA6:0> and <ALS> to I2CAR (<ALS>

= 0 when the

addressing format).

Subsequently, set 0 to <MST, TRX, BB>; 1 to <PIN>; 10 to <SBIM1:0>; and 0 to bits 0

and 1 in the SBICR2. The slave receiver mode is set.

Note:

The initialization of the serial bus interface circuit must be complete within the time

from all devices which are connected to the bus have initialized to any device does

not generate a start condition. If not, there is a possibility that another device starts

transferring before an end of the initialization of the serial bus interface circuit. Data

can not be received correctly.

(2) Start condition and slave address generation

Confirm a bus free status (when SIBSR<BB>

= 0).

Set the SBICR1<ACK> to 1 and specify a slave address and a direction bit to be

transmitted to the SBIDBR.

When the SBISR<BB> is 0, the start condition are generated and the slave address

and the direction bit which are set to the SBIDBR are output on a bus by wiring 1 to

the SBICR2<MST, TRX, BB> and PIN. An INTS2 interrupt request occurs at the 9th

falling edge of the SCL clock cycle, and the <PIN> is cleared to 0. The SCL pin is pulled

down to the low-level while the <PIN> is 0. When an interrupt request occurs, the

<TRX> changes by the hardware according to the direction bit only when an

acknowledge signal is returned from the slave device.

Note : Do not write a slave address to be output to the SBIDBR while data are transferred.

If data is written to the SBIDBR, data to been outputting may be destroyed.

Figure 3.10.12 Start Condition Generation and Slave Address Transfer

345678

A0R/ W

Slave address

+ Direction bit

Acknowledge signal

from a slave device

Start condition

SCL pin

SDA pin

<PIN>

INTS2

interrupt request

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