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6N135 Scheda tecnica(PDF) 4 Page - Toshiba Semiconductor |
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6N135 Scheda tecnica(HTML) 4 Page - Toshiba Semiconductor |
4 / 8 page 6N135,6N136 2007-10-01 4 Switching Specifications (unless otherwise specified. Ta = 25°C, VCC = 5V, IF = 16mA) Characteristic Symbol Test Circuit Test Condition Min. Typ. Max. Unit 6N135 RL = 4.1kΩ ― 0.2 1.5 μs Propagation delay time to logic low at output 6N136 tpHL 1 RL = 1.9kΩ ― 0.2 0.8 μs 6N135 RL = 4.1kΩ ― 1.0 1.5 μs Propagation delay time to logic high at output 6N136 tpLH 1 RL = 1.9kΩ ― 0.5 0.8 μs 6N135 IF = 0mA VCM = 10Vp−p RL = 4.1kΩ ― 1000 ― V / μs Common mode transient immunity at logic high level output (Note 10) 6N136 CMH 2 IF = 0mA VCM = 10Vp−p RL = 1.9kΩ ― 1000 ― V / μs 6N135 VCM = 10Vp−p RL = 4.1kΩ IF = 16mA ― −1000 ― V / μs Common mode transient immunity at logic low level output (Note 10) 6N136 CML 2 VCM = 10Vp−p RL = 1.9kΩ IF = 16mA ― −1000 ― V / μs Bandwidth (Note 11) BW ― RL = 100Ω ― 2 ― MHz (Note 8) DC current transfer ratio is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100%. (Note 9) Device considered a two −terminal device: Pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7 and 8 shorted together. (Note 10) Common mode transient immunity in logic high level is the maximum tolerable (positive) dvCM / dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a logic high state (i.e., VO > 2.0V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dvCM / dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO < 0.8V). (Note 11) The frequency at which the AC output voltage is 3dB below the low frequency asymptote. |
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